One known type of multi-processing system is the Symmetric Multi-Processing (SMP) system, in which multiple processors share memory. When developing software to run on a data processing apparatus, it is known to model the elements of the data processing apparatus as a software model, and then to run the software on that software model in order to test the operation of the software. Such an approach is often used where the software and hardware are being developed in parallel, and the software developers do not wish to wait until the hardware is finalised before being able to test the software being developed. By allowing an earlier testing of the software on the software model, certain potential problems with the software can be detected earlier than would otherwise be possible.
Within such a software model, the function of a processor can be modelled using an Instruction Set Simulator (ISS). Typically, an ISS is designed to replicate the function of a particular processor. However, such an ISS will typically execute each instruction atomically, and will not implement pipelining techniques. Hence, whilst an ISS can accurately replicate the function of a processor, it will not typically replicate accurately the timing that will be observed within the real processor being modelled by the ISS.
Within an SMP data processing apparatus, the memory system shared by the plurality of processors will typically be coherent memory, hence ensuring that the multiple processors see a consistent view of memory. However, the question of how consistent the view of that shared memory must be is dictated by the consistency model employed within the data processing apparatus. The consistency model sets out certain constraints which define when a processor must see a value that has been updated by another processor. A software program will define an original ordering of instructions, and the consistency model identifies what freedom the processor has to change that ordering. When considering the effects of different consistency models, consideration can be given to the orderings among read and writes performed by a single processor that are preserved by each consistency model. There are four such orderings:    1. R→R: a read followed by a read.    2. R→W: a read followed by a write, which is always preserved if the operations are to the same address, since this is an antidependence.    3. W→W: a write followed by a write, which is always preserved if they are to the same address, since this is an output dependence.    4. W→R: a write followed by a read, which is always preserved if they are to the same address, since this is a true dependence.
When employing a “strong ordering” consistency model (also referred to as a “sequential” consistency model), all four of the above orderings must be preserved, and this is hence equivalent to assuming a single centralised memory module that serialises all processor operations. Because ISSs typically execute each instruction in order and atomically, a software model of an SMP data processing apparatus will inherently apply a strongly-ordered consistency model.
However, the real SMP data processing apparatus being modelled will often employ a more relaxed consistency model, with the aim of enabling a performance gain to be realised. For example, a total store ordering (TSO) consistency model relaxes the ordering between a write and a read, hence eliminating the order W→R. Such models allow the buffering of writes with bypassing by reads, which occurs whenever the processor allows a read to proceed before it guarantees that an earlier write by that processor has been seen by all of the other processors. This consistency model allows a machine to hide some of the latency of a write operation.
If in addition non-conflicting writes are allowed to potentially complete out of order, by relaxing the W→W ordering, then the data processing apparatus is said to use a partial store ordering (PSO) consistency model. From an implementation view point, this allows pipelining or overlapping of write operations, rather than forcing one operation to complete before another.
Another major class of relaxed models eliminates the R→R and R→W orderings, in addition to the other two orders mentioned above. This model, which is called a weak ordering consistency model, does not preserve ordering among references, except for certain synchronisation operations. Although the R→R and R→W orderings are eliminated, the processor can only take advantage of this if it has non-blocking reads. In general, the major advantage of all weaker consistency models comes in hiding write latencies rather than read latencies.
A typical SMP data processing apparatus will implement a more relaxed memory consistency model than the earlier mentioned strongly ordered consistency model. Whilst testing of the software on the software model of the SMP apparatus will enable certain problems to be identified with the software, it will not enable any bugs to be identified which stem from incorrectly assuming a particular behaviour of memory consistency, when this is not appropriate having regard to the intended SMT apparatus. As an example, it may be the case that certain particular sequences within the software will only reliably execute correctly if a strongly ordered consistency model is present, and may occasionally operate incorrectly with any more weakly ordered consistency model. Such a bug would not typically be detected when running the software on a software model employing ISSs for each of the processors, due to the fact that those ISSs are inherently strongly ordered.
In general, such bugs arising from an incorrect assumption of a particular behaviour of memory ordering are very hard to detect and difficult to provoke. Accordingly, it would be desirable to provide an improved system for testing software to be run on an SMP data processing apparatus.